Materials
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0. Organization and Introduction (4.2 MB, rev 3)
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12.4. |
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1. Boolean Calculus (1.5 MB, rev 2)
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14.4. |
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2. Logic Synthesis (607 KB, rev 1)
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19.4. |
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3. Implicants and Prime Implicants (301 KB, rev 1)
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19.4. |
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4. Quine/McCluskey Algorithm (779 KB, rev 2)
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19.4. + 21.4. |
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5. Combinatorial Circuits (1.3 MB, rev 1)
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26.4. |
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6. Number Representations (780 KB, rev 2)
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28.4. |
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7. Arithmetic Circuits: Adders (1.8 MB, rev 3)
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28.4. + 3.5. + 5.5. |
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8. Arithmetic Circuits: Subtractors, Multipliers, ALU (1.3 MB, rev 1)
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5.5. + 10.5. |
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9. Sequential Circuits: Memory, Finite State Machines (1.5 MB, rev 2)
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10.5. + 12.5. |
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10. Verilog (1.2 MB, rev 1)
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17.5. |
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11. Instruction Set Architecture (1.5 MB, rev 1)
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19.5. + 24.5. |
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12. Microarchitecture at the Example of MIPS (1.6 MB, rev 1)
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24.5. |
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13. Performance: Basic Concepts (992 KB, rev 1)
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26.5. |
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14. Performance: Pipelining (1.6 MB, rev 1)
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26.5. + 31.5. |
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15. Performance: Advanced Pipelining Concepts (1.5 MB, rev 2)
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31.5. + 2.6. |
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16. Performance: Memory Hierarchy, Caches (3.7 MB, rev 2)
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2.6. + 7.6. + 14.6. |
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17a. ISA, μArchitecture, and Bad News from the Real World (1.7 MB, rev 1)
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14.6. + 16.6. |
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17b. Microarchitectural Attacks (3.9 MB, rev 2)
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14.6. + 16.6. |
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18. Operating Systems: Overview (90 KB, rev 1)
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21.6. |
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19. Limited Direct Execution (990 KB, rev 2)
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21.6. |
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20. I/O Devices (1.7 MB, rev 1)
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23.6. |
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21. Scheduling (1.2 MB, rev 1)
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23.6. + 28.6. |
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22. Memory Virtualization (812 KB, rev 1)
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28.6. |
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23. Paging (664 KB, rev 1)
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5.7. |
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24. Translation Lookaside Buffers (460 KB, rev 1)
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5.7. |
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25. Smaller Page Tables (381 KB, rev 1)
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7.7. |
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26. Swapping (827 KB, rev 1)
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7.7. |
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27. Memory Virtualization: Summary (728 KB, rev 1)
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12.7. |
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28. Disks and I/O Scheduling (795 KB, rev 1)
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12.7. |
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29. Flash-based Solid State Disks (465 KB, rev 1)
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14.7. |
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30. Error-detecting and Error-correcting Codes (698 KB, rev 2)
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14.7. + 19.7. |
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31. Recap (3.0 MB, rev 1)
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19.7. + 21.7. |
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