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Systems with Specialized Hardware
Format
course type / weekly hours: 2 h lectures + 2 h project (this is a hands-on session) + 1 h tutorials = 5 h (weekly) total workload: 75 h of classes + 195 h private study = 270 h (= 9 ECTS)
This course is comprised of lectures and project sessions. The lectures will introduce key concepts of accelerator design and project sessions will walk students through using open source tools to evaluate a rudimentary specialised system which they will later improve on. At the end of the course, students will work on an open-ended task: designing, implementing, and evaluating an improvement of their own choosing. This task will be accompanied with a light report explaining design choices and results.
Contents
The course is divided into three sections.
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Part A: Intro to Post Moore Acceleration
- Lectures: fundamentals of why accelerators matter in modern computing systems
- Labs: prerequisites for designing accelerators in this course: Verilog overview, tools summary
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Part B: System Bottleneck & Resource Evaluation
- Lectures: theory behind efficient accelerators, and how integration can either make or break a complete system
- Labs: hands-on experience with tools used to quantify performance & utilisation
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Part C: Design Tradeoffs & Optimisation
- Open-ended design exploration and improvement project.
- Lectures: techniques for shifting an accelerator's design along one or more axes, in order to achieve specific target metrics.
- Labs: Open office hours for guidance on the project
The projects will use the SimBricks full system simulation framework, providing in-depth control and visibility of the complete system, without the need for special hardware.
Kick-Off Meeting: TBD, xx:xx-xx:xx, E1 5 Room 029 MPI-SWS Building
Lectures: Fri, 12-14, E1 5 Room 029 MPI-SWS Building
Projects: Wed, 12-14, E1 5 Room 029 MPI-SWS Building
This advanced lecture is organised by the OS Group at MPI-SWS.
| Part | Lecture | Project | Date | Resources |
|---|---|---|---|---|
| A | Intro to Post-Moore Systems | |||
| System Design Terminologies | Verilog Primer | |||
| Accelerator Classification | Intro to Tools | |||
| B | Hardware Resource Utilisation | Evaluating Synthesis Output | ||
| Software Resource Utilisation | Memory Utilisation, Buffer Fill | |||
| Simbricks: Full System Evaluation | Using Simbricks | |||
| Specialising for Workloads | NS-3 Packet Generation Tests | |||
| C | Parallelism & Batching | Discuss Project Ideas | ||
| Pipelining | Additional Simbricks/Blueprint Features | |||
| Resource Sharing | From Design to ASIC | |||
| Dynamic Parallelism & Beyond | -- |
Disclaimer
The projects in this advanced lecture are relatively implementation-heavy compared to what you may be used to from other courses. You should also expect to engage in some hairy debugging (e.g. segmentation faults, and memory corruption) typical of low-level systems code. Please plan accordingly.
Requirements
This advanced lecture is open to senior Bachelor, Masters, and doctoral students. Ideally, students should have already taken courses on system architecture and operating systems. Bachelor students must have passed the basic courses on Programming 2 or equivalent. Proficiency in C/C++ programming (including low-level aspects such as pointers and memory management) and UNIX development tools (e.g., shell, make, gcc, gdb) is strictly required to pass this course. Basic Verilog knowledge will also be required for the projects, but this can be acquired or refreshed as part of the project. Please contact Antoine with questions about these requirements.
The language of the advanced lecture is English. All meetings and communication with the course staff will be conducted exclusively in English.