News
Milestone 2 is out!Written on 20.11.24 (last change on 20.11.24) by Artem Ageev We have released the second milestone today. You can find the requirement document Milestone2.md on gitlab in the ms2 branch. https://gitlab.cs.uni-saarland.de/os/swish-24ws/project/-/blob/ms2/Milestone2.md
Today's project session covered how to install OpenLane and how to generate… Read more We have released the second milestone today. You can find the requirement document Milestone2.md on gitlab in the ms2 branch. https://gitlab.cs.uni-saarland.de/os/swish-24ws/project/-/blob/ms2/Milestone2.md
Today's project session covered how to install OpenLane and how to generate plain verilog for Vortex. Please see the slides and/or watch the video if you have any questions.
For now don't worry if the synthesis reports any errors. |
Lectures & Project Sessions Now Start @ 12.05Written on 09.11.24 by Tejas Harith As discussed in the previous lecture (08.11.24), lectures and project sessions will now start at 12.05 and run till 13.35 to accommodate timing conflicts. If this timing does not work for you, please contact the course staff. See you all next Wednesday @ 12.05 ! (13.11.24) |
[ATTENTION]: Upstream Changes and Git Submodule ReposWritten on 01.11.24 by Tejas Harith Hi all, Thank you for getting started early on the project assignment and helping me iron out some rough edges! I have made a couple changes to the README where the `make check` vs `make tests` rules were inconsistent with what existed in the Makefile or `sudo` was missing from the chroot command.… Read more Hi all, Thank you for getting started early on the project assignment and helping me iron out some rough edges! I have made a couple changes to the README where the `make check` vs `make tests` rules were inconsistent with what existed in the Makefile or `sudo` was missing from the chroot command. Please pull the upstream changes from the class main project repo. Some of the changes will fix a broken PERF output for `printf` test. There was one important factor I overlooked which was committing changes inside the submodule. It is essential that you have your own submodule that you can organise and add branches to, so I have created new submodule repos for you all who registered for the "Project Git Repo" and you should have received an email for it. Since some of you may have already gotten started, instead of forcibly changing the submodule pointer for you, I have given instructions in the forum. Please see the forum response here. Please ask any follow up questions there. Pointing to your submodule and committing changes there will be necessary for the project milestone 1. Although your private submodules should already have all the necessary files for milestone 1, you should point to the public main submodule repo with
after which you can use
to sync up with new milestones to the submodule. Ultimately the gitlab ci/cd will still use your main project repo's `msX-submission` branch so make sure that the submodule is pointing to your `vortex-swish` repo and the correct commit/branch! Thanks for bearing with the bugs and I appreciate you all for bringing them to my attention! Tejas |
Zoom info page addedWritten on 30.10.24 (last change on 30.10.24) by Antoine Kaufmann In case anyone is trying to attend remotely today. We just added a page that has the info. Later today the recording info will be included there as well. |
Reminder: Register for Project Git RepoWritten on 28.10.24 (last change on 28.10.24) by Tejas Harith As mentioned in the previous lecture (whose recording will soon be uploaded), please remember to use the CMS "registration" > "Project Git Repo" so that we can launch a project repository for you with all the basic material. We will go over the project in the first project session which is this… Read more As mentioned in the previous lecture (whose recording will soon be uploaded), please remember to use the CMS "registration" > "Project Git Repo" so that we can launch a project repository for you with all the basic material. We will go over the project in the first project session which is this week! You will get an email when the repository has been generated. |
Reminder: Lecture Today in Room 029 Building E1 5Written on 25.10.24 (last change on 25.10.24) by Tejas Harith Walk into the MPI SWS building, all the way to the back. Take a right, and walk to the door at the end of the hall, past the bathrooms. Lecture zoom link: https://shlink.mpi-sws.org/os-24-lectures |
Reminder: No Project Session this week!Written on 23.10.24 (last change on 23.10.24) by Tejas Harith Project sessions start from next Wednesday 30.10. See you at lecture this Friday :). Note the location: E 1 5, the MPI-SWS building Rm 029. Starts at 12.15. |
Reminder: Kickoff Lecture Today!Written on 18.10.24 by Tejas Harith Welcome to the inaugural lecture of SwiSH W24/25!
We look forward to seeing you all in Rm 024, MPI-INF (E1 4). We will start at quarter past 12 and will go over course logistics as well as an introduction to Post-Moore systems! |
Systems with Specialized Hardware
Format
course type / weekly hours: 2 h lectures + 2 h project (this is a hands-on session) + 1 h tutorials = 5 h (weekly) total workload: 75 h of classes + 195 h private study = 270 h (= 9 ECTS)
This course is comprised of lectures and project sessions. The lectures will introduce key concepts of accelerator design and project sessions will walk students through using open source tools to evaluate a rudimentary specialised system which they will later improve on. At the end of the course, students will work on an open-ended task: designing, implementing, and evaluating an improvement of their own choosing. This task will be accompanied with a light report explaining design choices and results.
Contents
The course is divided into three sections.
-
Part A: Intro to Post Moore Acceleration
- Lectures: fundamentals of why accelerators matter in modern computing systems
- Labs: prerequisites for designing accelerators in this course: Verilog overview, tools summary
-
Part B: System Bottleneck & Resource Evaluation
- Lectures: theory behind efficient accelerators, and how integration can either make or break a complete system
- Labs: hands-on experience with tools used to quantify performance & utilisation
-
Part C: Design Tradeoffs & Optimisation
- Open-ended design exploration and improvement project.
- Lectures: techniques for shifting an accelerator's design along one or more axes, in order to achieve specific target metrics.
- Labs: Open office hours for guidance on the project
The projects will use the SimBricks full system simulation framework, providing in-depth control and visibility of the complete system, without the need for special hardware.
Kick-Off Meeting: Fri Oct 18, 12-14, E1 4 Room 024 MPI-INF Building
Lectures: Fri, 12-14, E1 5 Room 029 MPI-SWS Building
Projects: Wed, 12-14, E1 5 Room 029 MPI-SWS Building
This advanced lecture is organised by the OS Group at MPI-SWS.
Lectures
| Part | Lecture | Project Session | Lecture Date | Project Session Date | MS | Resources |
|---|---|---|---|---|---|---|
| A | Intro to Post-Moore Systems | 18.10 | ||||
| System Design Terminologies | Verilog & Project Primer | 25.10 | 30.10 | 1 | Dark Silicon | |
| Holiday: All Saints | Intro to Hardware Design Tools | -- | 06.11 | 1 | ||
| Accelerator Classification Part 1 | Devices, Drivers & Interfacing | 08.11 | 13.11 | 1 | ||
| B | Accelerator Classification Part 2 | Evaluating Synthesis Output | 15.11 | 20.11 | 2 | |
| Hardware Resource Utilisation | DMA | 22.11 | 27.11 | 2 | ||
| Software Resource Utilisation | Intro to Simbricks | 29.11 | 04.12 | 3 | ||
| Specialising for Workloads | Memory Utilisation, Buffer Fill | 06.12 | 11.12 | 3 | ||
| C | Pipelining, Parallelism & Batching | Discuss Project Ideas | 13.12 | 18.12 | Fin | |
| -- | Additional Simbricks/Blueprint Features | 20.12 | 08.01 | Fin | ||
| Resource Sharing & Dynamic Parallelism | From Design to ASIC | 10.01 | 15.01 | Fin | ||
| Beyond CMOS | Special Topics: TBA | 17.01 | 22.01 | Fin | ||
| Guest Lecture: TBA | Special Topics: TBA | 24.01 | Fin | |||
| TBA | -- | 31.01 | Fin | |||
| End | -- | -- | 07.02 |
Milestones
| MS | Topic | Release | Due | Pts |
| 1 | Measuring Baselines | 30.10 | 19.11 | 10 |
| 2 | Design Tradeoffs | 20.11 | 10 | |
| 3 | Orchestrating Data | 10 | ||
| Final | System Improvement | 30 |
Disclaimer
The projects in this advanced lecture are relatively implementation-heavy compared to what you may be used to from other courses. You should also expect to engage in some hairy debugging (e.g. segmentation faults, and memory corruption) typical of low-level systems code. Please plan accordingly.
Requirements
This advanced lecture is open to senior Bachelor, Masters, and doctoral students. Ideally, students should have already taken courses on system architecture and operating systems. Bachelor students must have passed the basic courses on Programming 2 or equivalent. Proficiency in C/C++ programming (including low-level aspects such as pointers and memory management) and UNIX development tools (e.g., shell, make, gcc, gdb) is strictly required to pass this course. Basic Verilog knowledge will also be required for the projects, but this can be acquired or refreshed as part of the project. Please contact Antoine with questions about these requirements.
The language of the advanced lecture is English. All meetings and communication with the course staff will be conducted exclusively in English.