Second Project Milestone Released

Written on 21.11.23 by Antoine Kaufmann

See here:

First Project Released

Written on 09.11.23 by Antoine Kaufmann

See here:

Weekly Meeting: Fridays 13 - 14h / 14 - 15h

Written on 05.11.23 by Antoine Kaufmann

Our weekly meeting will be on Fridays from 13:15-14:00 or 14:15-15:00. You can join one or both of these slots.

Accelerating Applications with Specialized Hardware

In this seminar, you will learn about various aspects of hardware acceleration, primarily through a series of hands-on projects. The projects focus on different aspects of the complete system, such as modifying an application to take advantage of an accelerator, implementing necessary software components to interact with the hardware, optimizing the interface between software and hardware, and even implementing (parts of) a hardware accelerator. Overall, the main goal is for you to completely understand the full picture of all system components involved and their interactions. The focus is on the principles and fundamental constraints rather than specific tools or applications.

The projects will use the SimBricks full system simulation framework, providing in-depth control and visibility of the complete system, without the need for special hardware.

Kick-Off Meeting: Mon, 30. Oct, 13:15-14:00, E1 5 Room 105 MPI-SWS Building

Regular Meeting: Fridays, 13:15-15:00, E1 5 Room 105 MPI-SWS Building (no need to attend the full 2h)

This seminar is organized by the OS Group at MPI-SWS.



The seminar primarily revolves around the series of projects, these are what you will be spending most of your time on. We will meet in-person once a week, primarily to discuss project milestones, questions,  and ongoing progress (remote attendance is possible in justified cases, contact Antoine). The instructor and a teaching assistant will also available for discussing questions or problems asynchronously via the discussion board. Your project milestone submissions will be graded through automated tests (that you can run yourself too). Additionally, the final project milestone comprises an open-ended design component, for which each student will prepare a brief description and a short presentation for the rest of the class in the last week. The seminar grade will be calculated as a weighted score of 80% for the project milestone tests, and 20% for the report and presentation.



The projects in this seminar are relatively implementation-heavy compared to what you may be used to from other courses. You should also expect to engage in some hairy debugging (e.g. segmentation faults, and memory corruption) typical of low-level systems code. Please plan accordingly.



This seminar is open to senior Bachelor, Masters, and doctoral students. Ideally, students should have already taken courses on system architecture and operating systems. Bachelor students must have passed the basic courses on Programming 2 or equivalent. Proficiency in C/C++ programming (including low-level aspects such as pointers and memory management) and UNIX development tools (e.g., shell, make, gcc, gdb) is strictly required to pass this course. Basic Verilog knowledge will also be required for the projects, but this can be acquired or refreshed as part of the project. Please contact Antoine with questions about these requirements.

The language of the seminar is English. All meetings and communication with the course staff will be conducted exclusively in English.

Privacy Policy | Legal Notice
If you encounter technical problems, please contact the administrators.